1. Field of the Invention
This invention relates to a memory cell for use in a multi-port RAM in which data are read out synchronous with a clock signal. In particular, it relates to a memory cell for use in a multi-port RAM which is used as an element for constructing a high speed logic LSI, such as a processor.
2. Description of the Prior Art
An example of a multi-port RAM which is used, for example, in a processor system and operated synchronously with a clock signal, is shown in FIG. 4.
The RAM shown in FIG. 4 has read only ports A and B, and a write only port C. This RAM also has word lines AWL, BWL, and CWL, and bit lines ABL, BBL, CBL, and /CBL for a memory cell 1. Word line AWL and bit line ABL correspond to port A, word line BWL and bit line BBL correspond to port B, and word line CWL and bit lines CBL and /CBL correspond to port C.
Memory cell 1 is comprised of the following: a flip flop (F/F) circuit 2 to memorize data obtained from write only bit lines; a first series of transistors including N channel FET (referred to as N-FET, below) A1 and N-FET A2; and a second series of transistors including N-FET B1 and N-FET B2. In this memory cell, the gate of said N-FET A1 is connected with a node NA of F/F circuit 2, and the gate of N-FET A2 is connected with word line AWL. These two N-FETs are inserted between bit line ABL and the ground in order to read out data from port A. In the same way, N-FET B1 and N-FET B2 are provided corresponding to node NB and word line BWL and inserted between bit line BBL and the ground.
Stored data in memory cell 1 are read out through input-output circuit 3, in which an N-FET A3, a P channel FET (referred to as P-FET, below) A4, an N-FET B3, and a P-FET B4 are provided. These, transistors perform pre-charge for bit lines ABL and BBL in synchronism with the clock signal.
In memory cell 1, each word line AWL, BWL, or CWL is selected by address decoder 4. In other words, address decoder 4 decodes each port address signal under the control of the clock signal and selectively indicates a corresponding word line.
Next, the data read out processing from port A will be explained in the structure with reference to the timing chart shown in FIG. 5.
During a period in which clock signal CLK is in a high level, word line AWL has a low level, and FETs A3 and A4 for pre-charge become conductive. As a result, bit line ABL becomes a high level and is allowed to be pre-charged.
If the clock signal becomes low level in the situation as shown in FIG. 5, the address signal from port A, which has been fixed and given to address decoder 4 at the very early stage in the high level state of the clock signal, is decoded by address decoder 4. At the same time, FETs A3 and A4 for pre-charge become non-conductive.
As the result of the decoding, that is, when word line AWL is selected to be a high level in the condition where high level data are stored in node NA of memory cell 1, N-FETs A1 and A2 become conductive. Thus, bit line ABL becomes conductive, allowing port A data having a high level to be read out through input-output circuit 3.
In such a read out processing, the address signal in port A is fixed considerably before the clock signal becomes a low level, that is, an enable state in which a read out processing is allowed. If the clock signal is in a high level, the fixed address signal cannot be decoded to make word line AWL be a high level, because bit line ABL has already been pre-charged. In other words, the decoding of an address signal is allowed only when the clock signal is in an enable state because it is controlled by the clock signal.
As described above in a prior art multi-port RAM shown in FIG. 4, the read out processing is carried out is synchronism with the clock signal. In other words, although an address signal has been fixed and given to an address decoder considerably before the clock signal reaches the enable state, the decoding of the address signal to selectively specify a certain word line should be postponed until the clock signal reaches the enable state. Accordingly, the access time (t.sub.acc), which begins when the clock signal reaches the enable state and ends when data are read out, includes the address decoding time, thus causing a difficulty in executing a read out processing with high speed.